1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device comprising a test circuit, and a method of operation thereof.
2. Description of the Background Art
In recent years, increase in testing time has become significant as the size of semiconductor devices has increased. As a technique to reduce testing time drastically, a line mode test is proposed in 1989 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 244-245. According to this line mode test, all the memory cells connected to one word line are tested simultaneously to allow testing of a number of bits at one time. This is expected to reduce testing time significantly.
FIG. 31 shows the structure of main components of a conventional dynamic type semiconductor memory device having a line mode test function.
Referring to FIG. 31, a plurality of bit line pairs BL, BL and a plurality of word lines WL are arranged perpendicular to each other, with a memory cell MC at each crossing point. The plurality of word lines WL are connected to a row decoder 3 comprising a decoder 31 and a word driver 32. A sense amplifier 50 is connected to each bit line pair BL, BL. Each bit line pair BL, BL is connected to input/output line pair I/O, I/O via N channel MOS transistors 121, 122 and N channel MOS transistors 125, 126. Transistors 121, 122, 125 and 126 implement a transfer gate. The gates of transistors 125 and 126 are supplied with a column selecting signal Yi (i=1, 2, . . . ) from a column decoder 4. A comparison circuit 100 and a latch circuit 110 are provided corresponding to each bit line pair BL, BL.
Row decoder 3 is responsive to an externally applied row address signal RA to select one of the plurality of word lines WL, to raise the potential thereof to a H level. A column decoder 4 is responsive to an externally applied column address signal CA to select one of the plurality of bit line pairs BL, BL to provide column selecting signal Yi of a H level to the gates of the corresponding transistors 125 and 126. Thus, one memory cell MC is selected, whereby data is written into the selected memory cell MC via input/output line pair I/O, I/O, or data stored in the selected memory cell MC is read out to an external source via input/output line pair I/O, I/O.
The line mode test will be explained hereinafter. In line mode test, an externally applied expected data is first stored in a latch circuit 110. Data read out from the memory cell MC connected to the selected word line WL and the expected data stored in latch circuit 110 are compared by a comparison circuit 100. Hence, the testing of a plurality of memory cells MC connected to one word line WL is performed at one time.
First, writing test data into memory cell MC will be explained.
Transistors 125 and 126 selected by column decoder 4 are turned on. This causes external test data applied through input/output line pair I/O, I/0 to be transmitted to nodes NA and NB. This test data is stored in latch circuit 110. The test data stored in latch circuit 110 is the expected data at the time of testing. Signal TR is at a L level at this time. Transistors 121 and 122 are off and test data in nodes NA and NB are not transmitted to bit line pair BL, BL. By sequentially selecting a plurality of pairs of transistors 125 and 126 by column decoder 4, test data is sequentially stored in a plurality of latch circuits 110.
Signal TR then rises to a H level. This turns transistors 121 and 122 on. One of the plurality of word lines WL is selected by row decoder 3. This causes the test data stored in latch circuit 110 to be written into each memory cell MC connected to the selected word line WL. By sequentially selecting a plurality of word lines WL by row decoder 3, test data is written into all the memory cells MC.
The read out of the test data stored in memory cell MC, and the comparison of the read out test data with the expected data will be explained hereinafter.
One of the plurality of word lines WL is selected by the row decoder 3. This causes test data to be read out from the memory cell MC connected to the selected word line WL into the corresponding bit line pair BL, BL. The read out test data is amplified by the corresponding sense amplifier 50.
Signal LTE rises to a H level, while signal TR is still at the L level. This turns on N channel MOS transistors 123 and 124. As a result, the test data read out from each memory cell are transmitted to the corresponding comparison circuits 100. Each comparison circuit 100 is supplied with the expected data stored in latch circuit 110 via nodes NA, NB and NV, NW. Each comparison circuit 100 compares the test data read out from memory cell MC with the expected data stored in latch circuit 110 to provide the comparison result to detection line LTS.
When the test data read out from memory cell MC matches the expected data stored in latch circuit 110 in all comparison circuits 100, the potential of detection line LTS is maintained at a H level. If the test data read out from memory cell MC does not match the expected data stored in latch circuit 110 in at least one comparison circuit 110, the potential of detection line LTS is discharged to a L level.
FIG. 32 shows in detail the structure of comparison circuit 100 and latch circuit 110 of FIG. 31.
Comparison circuit 100 comprises N channel MOS transistors 101-104. Latch circuit 110 comprises N channel MOS transistors 111, 112 and P channel MOS transistors 113, 114.
When column selecting signal Yi attains a H level by column decoder 4 (FIG. 31), transistors 125 and 126 are turned on. This causes externally applied test data to be transmitted to nodes NA and NB via input/output line pair I/O, I/O and to be stored in latch circuit 110. When signal CRE attains a H level and signal CRE attains a L level, N channel MOS transistor 127 and P channel MOS transistor 128 are each turned on. This causes the potential of H level of either nodes NA or NB to be set to the supply level, and the potential of the L level set to the ground level.
At the time of testing, the potential of node NC is in advance set to a L level, by turning on N channel MOS transistor 103 with signal LTR. The potential of detection line LTS is set to a H level in advance.
When signal LTE rises to a H level while signal TR remains at a L level, transistors 123 and 124 are turned on. This causes nodes NE and NF of bit line pair BL, BL to be connected to comparison circuit 100. For example, if the potential of node NA is at a H level, and the potential of node NB is at a L level, transistor 102 is on and transistor 101 is off.
If correct test data is read out from memory cell MC, the potential of node NE is at a H level, and the potential of node NF is at a L level. The potential of node NC remains at a L level. Therefore, N channel MOS transistor 104 is off, and the potential of node ND of detection line LTS remains at a H level.
If erroneous test data is read out from memory cell MC, the potential of node NE is at a L level, and the potential of node NF is at the H level. The potential of node NC therefore attains a H level to turn on transistor 104. This causes the potential of node ND of detection line LTS to drop to L. Hence, error is detected.
Although test operation regarding one pair of bit lines BL and BL is described in FIG. 32, the above-mentioned operation is carried out for all bit line pairs BL, BL at one time. Even if only one erroneous test data is read out from one memory cell MC, node ND of detection line LTS drops to a L level.
The line mode test of a conventional dynamic type semiconductor memory device can be summarized as follows.
First, an external applied test data is stored in a plurality of latch circuits 110. Then, test data from a plurality of latch circuits 110 are written into a plurality of memory cells connected to a selected word line WL at one time. This writing operation is repeated for each word line.
Then, test data are read out from a plurality of memory cells MC connected to the selected word line WL simultaneously. The read out test data are compared with the data stored in latch circuits 110. This read out operation and comparison operation are also carried out for each word line.
Line mode test is completed when the test data read out from memory cell MC matches the expected data stored in latch circuit 110 in each comparison operation. If the test data read out from memory cell MC does not match the expected data stored in latch circuit 110 even in one comparison operation, an error flag of a L level is provided from detection line LTS.
It is necessary to provide a plurality of latch circuits and a plurality of comparison circuits corresponding to the number of plurality of bit line pairs for carrying out the line mode test in the above conventional semiconductor memory device. This arrangement disadvantageously consumes increased layout area.
It was necessary to carry out one writing operation, for each bit line pair in writing the test data to the plurality of latch circuits and bit line pairs. Therefore, reduction in testing time could not be expected.